Commit 41d9e357 authored by GuentherMartin's avatar GuentherMartin
Browse files

DSP_Lib changes:

 - new version V1.5.5
 - reworked DSP library source files
     added macro ARM_MATH_LOOPUNROLL
     removed macro UNALIGNED_SUPPORT_DISABLE
     relpaced arm_bitreversal2.S with C version
     added const-correctness
     replaced SIMD pointer construct with memcpy solution
 - reworked DSP library documentation
 - moved DSP libraries to folder ./DSP/Lib
 - ARM DSP Libraries are built with ARMCLANG
 - Added DSP Libraries Source variant
parent 9d0d7635
......@@ -8,6 +8,21 @@
<url>http://www.keil.com/pack/</url>
<releases>
<release version="5.5.0-dev55">
Active development ...
DSP_Lib:
- new version V1.5.5
- reworked DSP library source files
added macro ARM_MATH_LOOPUNROLL
removed macro UNALIGNED_SUPPORT_DISABLE
relpaced arm_bitreversal2.S with C version
added const-correctness
replaced SIMD pointer construct with memcpy solution
- reworked DSP library documentation
- moved DSP libraries to folder ./DSP/Lib
- ARM DSP Libraries are built with ARMCLANG
- Added DSP Libraries Source variant
</release>
<release version="5.5.0-dev5">
Development Snapshot ...
CMSIS-Driver:
......@@ -3053,7 +3068,7 @@ and 8-bit Java bytecodes in Jazelle state.
</component>
<!-- CMSIS-DSP component -->
<component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
<component Cclass="CMSIS" Cgroup="DSP" Cvariant="Library" Cversion="1.5.5" condition="CMSIS DSP">
<description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
<files>
<!-- CPU independent -->
......@@ -3062,101 +3077,122 @@ and 8-bit Java bytecodes in Jazelle state.
<!-- CPU and Compiler dependent -->
<!-- ARMCC -->
<file category="library" condition="CM0_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM0_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM1_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM1_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM3_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM3_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_SP_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_DP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_DP_BE_ARMCC" name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM23_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_NODSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_DSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_NODSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_DSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
<!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC" name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
<file category="library" condition="CM0_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM0_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM1_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM1_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM0b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM3_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM3l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM3_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM3b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4lf_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM4bf_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7l_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7b_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7lfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_SP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7bfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_DP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7lfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM7_DP_BE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_cortexM7bfdp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM23_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM33_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="CM35P_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MBL_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MBLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLl_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLld_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfsp_math.lib" src="CMSIS/DSP/Source/ARM"/>
<!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLlfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
<!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC" name="CMSIS/DSP/Lib/ARM/arm_ARMv8MMLldfdp_math.lib" src="CMSIS/DSP/Source/ARM"/-->
<!-- GCC -->
<file category="library" condition="CM0_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM1_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM3_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM4_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM7_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM7_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM7_DP_LE_GCC" name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM23_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_NODSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_DSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
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<file category="library" condition="CM35P_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM35P_NODSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM35P_DSP_SP_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC" name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
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<file category="library" condition="CM1_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM0l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM3_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM3l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM4_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM4l_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM4_FP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM4lf_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM7_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_cortexM7l_math.a" src="CMSIS/DSP/Source/GCC"/>
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<file category="library" condition="CM23_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM33_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
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<file category="library" condition="CM35P_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM35P_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="CM35P_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MBL_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
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<!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC" name="CMSIS/DSP/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
<!-- IAR -->
<file category="library" condition="CM0_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM0_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM1_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM1_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM3_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM3l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM3_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM3b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM4l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM4b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_FP_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_DP_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_DP_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_SP_BE_IAR" name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM23_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
<!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
<file category="library" condition="CM0_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM0_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM1_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM1_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM3_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM3l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM3_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM3b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_FP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4lf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM4_FP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM4bf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7l_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7b_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_DP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7lf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_DP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7bf_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7ls_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM7_SP_BE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM7bs_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM23_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM33_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="CM35P_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MBL_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MBLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLl_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLld_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<file category="library" condition="ARMv8MML_DSP_SP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
<!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLlfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
<!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
</files>
</component>
<component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cversion="1.5.5" condition="CMSIS DSP">
<description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
<file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
<!-- RTX sources (core) -->
<file category="source" name="CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/CommonTables/CommonTables.c"/>
<file category="source" name="CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c"/>
<file category="source" name="CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c"/>
</files>
</component>
......
......@@ -12,7 +12,7 @@ LOG OFF /* Turn off Logging by defau
BK * /* Remove existing breakpoints. */
INCLUDE ../../Common/JTest/jtest_fns.ini /* Load the JTEST helper functions */
INCLUDE ../../Common/JTest/jtest_log_FVP.ini /* Include a log file if specified by jtest_log.ini */
INCLUDE ../../Common/JTest/jtest_log_FVP.ini /* Include specified log file */
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */
......
......@@ -17,12 +17,12 @@ INCLUDE ../../Common/JTest/jtest_log_Simulator.ini /* Include specified log fil
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */
BS test_start , 1, "coverage_clear(); test_start_msg();"
BS test_end , 1, "coverage_msg(); test_end_msg();"
BS test_start , 1, "test_start_msg();"
BS test_end , 1, "test_end_msg();"
BS group_start , 1, "group_start_msg();"
BS group_end , 1, "group_end_msg();"
BS dump_str , 1, "dump_str_fn();"
BS dump_data , 1, "dump_data_fn();"
//BS dump_data , 1, "dump_data_fn();"
BS exit_fw , 1, "break_fn(); debug_clean_fn(); log_off_fn();"
debug_setup_finished_msg() /* Output a message to let the output
......
/* This demonstrates how to setup a Debugger '*.ini' file to interface with the
* C-code using the JTEST test framework.
*/
MAP 0x00000000, 0x001FFFFF EXEC READ /* 2048K Flash */
MAP 0x20000000, 0x201FFFFF READ WRITE /* 2048K RAM */
LOAD %L INCREMENTAL
RESET /* Reset the target processor */
LOG OFF /* Turn off Logging by default. */
BK * /* Remove existing breakpoints. */
INCLUDE ../../Common/JTest/jtest_fns.ini /* Load the JTEST helper functions */
INCLUDE ../../Common/JTest/jtest_log_Simulator.ini /* Include specified log file */
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */
BS test_start , 1, "coverage_clear(); test_start_msg();"
BS test_end , 1, "coverage_msg(); test_end_msg();"
BS group_start , 1, "group_start_msg();"
BS group_end , 1, "group_end_msg();"
BS dump_str , 1, "dump_str_fn();"
BS dump_data , 1, "dump_data_fn();"
BS exit_fw , 1, "break_fn(); debug_clean_fn(); log_off_fn();"
debug_setup_finished_msg() /* Output a message to let the output
parser know that setup has
finished. */
G /* Start the Tests */
......@@ -140,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"../cortexM0l_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"../cortexM0l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -293,7 +293,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"../cortexM3l_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"../cortexM3l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -446,7 +446,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"../cortexM4l_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"../cortexM4l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -619,7 +619,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -792,7 +792,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7l_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -965,7 +965,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfsp_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1118,7 +1118,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfdp_config.txt" -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfdp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1286,7 +1286,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1439,7 +1439,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1607,7 +1607,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1775,7 +1775,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......@@ -1943,7 +1943,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
......
......@@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>ARMCM0</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -338,7 +338,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -860,7 +860,7 @@
<TargetCommonOption>
<Device>ARMCM3</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -1182,7 +1182,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -1704,7 +1704,7 @@
<TargetCommonOption>
<Device>ARMCM4</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -2026,7 +2026,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -2548,7 +2548,7 @@
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -2870,7 +2870,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -3392,7 +3392,7 @@
<TargetCommonOption>
<Device>ARMCM7</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -3714,7 +3714,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -4236,7 +4236,7 @@
<TargetCommonOption>
<Device>ARMCM7_SP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -4558,7 +4558,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -5080,7 +5080,7 @@
<TargetCommonOption>
<Device>ARMCM7_DP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -5402,7 +5402,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -5925,7 +5925,7 @@
<TargetCommonOption>
<Device>ARMv8MBL</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -6247,7 +6247,7 @@
<MiscControls>-fhonor-nans</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -6770,7 +6770,7 @@
<TargetCommonOption>
<Device>ARMv8MML</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -7092,7 +7092,7 @@
<MiscControls>-fhonor-nans</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
......@@ -7615,7 +7615,7 @@
<TargetCommonOption>
<Device>ARMv8MML_SP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.0-dev57</PackID>
<PackID>ARM.CMSIS.5.5.0-dev52</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(SFPU) TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
......@@ -7937,7 +7937,7 @@
<MiscControls>-fhonor-nans</MiscControls>
<Define></Define>